AMD introduces its new generation of server processors EPYC 8004
September 18, 2023
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The Sunnyvale giant introduced the new EPYC 8004, a family of next-generation processors for servers and data centers that represent a clear commitment to specialization tackle different workloads
The Sunnyvale giant introduced the new EPYC 8004, a family of next-generation processors for servers and data centers that represent a clear commitment to specialization tackle different workloads more effectively.
To better understand where the EPYC 8004 is located and what its purpose is, it is necessary to review different versions of new generation EPYC processors that AMD currently has in its catalog:
AMD EPYC Genoa, based on the Zen 4 architecture and configured with up to 96 cores and 192 threads per socket. Designed for general use.
AMD EPYC Bergamo, based on the Zen 4c architecture and configured with up to 128 cores and 256 threads per socket. Designed for cloud computing.
AMD EPYC Genoa-X, based on the Zen 4 architecture but with more 3D-stacked L3 cache and configured with up to 96 cores and 192 threads per socket. Ideal for more technical tasks that can take advantage of a larger cache.
AMD EPYC Siena, which are the new 8004s that AMD just introduced, which are aimed at intelligent edge computing.
AMD EPYC 8004: values
The new AMD EPYC Siena processors are designed to offer a excellent energy efficiencybalanced performance, very high power per watt valuewhich translates into lower cost of ownership and also allows for more flexible designs thanks to its thermal optimizations.
You can see in the attached picture differences that exist between the AMD EPYC 9004 processors, which include both Genoa, Bergamo and Genoa-X, and the AMD EPYC 8004, which includes the new Siena. This new generation:
It will be available in configurations between 8 cores and 16 threads and 64 cores and 128 threads.
It can only be configured on the single socket model.
It uses the Zen 4c architecture, in which each chiplet consists of 8 cores and 16 threads, 1 MB of L2 cache per core and 16 MB of L3 cache shared by all cores.
They will have a TDP of 70 to 225 watts.
They will support DDR5 memory configurations in up to 6 channels at 4800 MHz.
PCIe Gen5 support and a maximum of 96 lanes.
Support for CXL 1.1+ standard and 48 lines.
It will support RDIMMs.
As I have told you on previous occasions, the Zen 4c architecture is a slightly improved version of the Zen 4 architecture, which essentially maintains the most important keys of this, including the ISA subsystem, L1 and L2 caches and IPC, so the only important difference is the reduction of the L3 cache, which goes from 32 MB per chiplet to 16 MB per chiplet.
In the attached image, we can see that Siena offers a clearly defined value compared to Genoa and that it focuses on improving total cost of ownership and energy efficiency. That’s what makes it a specialized solution and what it gives you an important differentiating value compared to the rest of the options that AMD has in its catalog.
To make identification easier, AMD shared a screenshot where we can see the most important keys in this sense based on his nomenclature. The 8 indicates the family or range it fits into, the second number indicates the number of cores within the series, the third number indicates the performance level (the higher the higher), and the last number indicates the generation. The last two letters indicate peculiarities, such as whether it is a single-socket model.
A more detailed view and available models
Look carefully at the image below these lines. In it we can see a complete breakdown of all the components that make up the EPYC 8004 with 64 cores and 128 threads. We have a total of 8 chiplets with 8 cores and 16 threads processing each of these that integrate 16 MB of L3 cache, leaving us with a total of 128 MB of L3 cache. It is important that you remember this each chip has access only to its L3 cache.
CPU chips are manufactured in TS 5nm nodeMCand the I/O chiplet is manufactured in 6nm node also from TSMC. The entire connectivity subsystem is integrated into the latter, including DDR5 memory controllers, PCIe Gen5 interface and third-generation Infinity Fabric. As I told you, it supports 6-channel DDR5 configurations at 4800MHz with a maximum capacity of 1152TB and offers up to 96 PCIe Gen5 lanes and 48 CXL 1.1+ lanes.
The entire AMD EPYC 8004 family has a kit AVX-512 manualdispose of SMT (two threads per core), has a turbo mode that dynamically adjusts operating frequencies, integrates the latest Infinity Fabric interconnect system and has protective technology AMD Infinity Guardand security at the hardware level.
These processors use a new socket with smaller design, SP6. In the last image, you can see a list of all the models that AMD will release under the EPYC 8004 series. The most basic configuration will have 8 cores and 16 threads, and from there it will scale in increments of 8 cores and 16 threads up to a maximum of 64 cores and 128 threads.
Performance data provided by AMD
To better demonstrate what its new EPYC 8004 processors can do, Sunnyvale showed us some performance data, and we can see that the EPYC 8534P processor It is able to almost double the power per watt 60-core Intel Xeon Platinum 8490H.
Obviously, the results depend a lot on the test we use and the task to be performed. When transcoding we see that the power per core is 16% higher with EPYC 8324P compared to the Intel Xeon Gold 6421N. There’s no doubt that the EPYC 8004s stand out above all for value in terms of consumption and cost of ownership, thanks to their great performance per watt consumed, but as we’ve seen, they’re no slouch in raw power either.
AMD has confirmed that Dell, Lenovo and Supermicro will be among the first OEMs to offer platforms configured with these new processors, and in a single image showed off the impressive ecosystem of partners it’s creating as part of its commitment to the intelligent Edge, where we can see names as important as VMWare, Fujitsu, HPE, Cisco and Oracleamong others.
Donald Salinas is an experienced automobile journalist and writer for Div Bracket. He brings his readers the latest news and developments from the world of automobiles, offering a unique and knowledgeable perspective on the latest trends and innovations in the automotive industry.