Zen 5 will be AMD’s next architecture for the x86 CPU sector. We’ve already seen information that guaranteed this new generation would reach a major performance improvementbut thanks to the new leak, we have more interesting details to share with you with a clear and simple explanation of each key.

It is important that you keep in mind that nothing that we will see below is confirmed and that there are some details that have dubious credibility, although at the same time we found more data that makes sense. It is precisely for the latter that I decided to dedicate an article to this information, because some of the things it states could absolutely be fulfilled.

Zen 5: two versions and up to 16 cores per chip

We’re starting with Zen 5 because this is the first architecture to hit the market, so we believe we know it best right now. It will be produced in TSMC 4nm nodea process that represents a minor evolution compared to the 5nm node that uses the Zen 4 architecture and that will improve consumption and performance values.

This architecture will retain the basics of the current chiplet, which means we can expect a count of 8 cores and 16 threads and a total of 32MB of L3 cache. Thanks to improvements at the microarchitecture level, we can expect a jump in terms of IPC between 14% and 26% compared to Zen 4. The average is around 20%, which means that Zen 5 would be one of the biggest generational leaps in AMD history.

On the other hand, we have the Zen 5c, which will make the jump to TSMC’s 3nm node, which means that you can significantly reduce the size of the transistors, leaving more space on the chip. It will also improve performance and energy consumption values. In theory, AMD will use this jump to the 3nm node to completely redesign the CCD, also known as the CPU chiplet, and increase the maximum number of cores from 8 to 16.

This is something very interesting, but we must remember that for the integration of 16 cores in one CCD will also be necessary reduce the amount of L3 cache, something we’ve actually already seen with the Zen 4c processors. By that I mean Zen 5c will have 16 cores per CCD, but the total size of the L3 cache should only be 32MB, not 64MB. Considering the weight that L3 cache has in games, it is clear that this version will not be aimed at the mainstream consumer market.

Zen 6: smaller jump in IPC, but bigger in multithreading

This architecture will be the successor to Zen 5 and is said to be produced in two different nodes, 3nm and 2nm. The Zen 6 will use a 3nm node, while the 2nm node could be limited to the Zen 6c. Improvements we can expect in CPI terms it is 10% generation after generation, i.e. compared to the immediately preceding generation.

The source assures that AMD will introduce important design changes with Zen 6 to achieve this improving latency and efficiency this brings this architecture closer to levels that would theoretically only be possible with a monolithic design. To achieve this, we are talking about a configuration in which The CCD units would be stacked on top of the IODand this will connect the CCD directly to the silicon bridges. The new generation of Infinity Fabric will also be used.

With Zen 6, we can also expect the use of new encapsulation and packaging technologies and an increase in the maximum number of cores per CCD unit, which It could take us up to 16 cores for this architecture, up to 32 cores for Zen 6c. Again, remember that the latter would have half the L3 cache, and therefore its performance in applications that depend on said cache, such as games, would be lower.

Both Zen 5 and Zen 6 They should be compatible with the AM5 socket. We don’t expect a refresh of the platform from AMD until the launch of Zen 7, the architecture that will use the new socket, although this will not mean the immediate end of the AM5 socket, in fact the opposite will happen. I believe there will be a period of coexistence between this socket and the next one from AMD for a few years, as is happening right now with AM4 and AM5 sockets.