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SMIC working on 3nm process despite US sanctions

  • December 24, 2023
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A new Nikkei report says Chinese chipmaker SMIC is developing 3nm manufacturing techniques despite significant hardware challenges caused by US sanctions. A chipmaker has been denied access to

SMIC working on 3nm process despite US sanctions

A new Nikkei report says Chinese chipmaker SMIC is developing 3nm manufacturing techniques despite significant hardware challenges caused by US sanctions. A chipmaker has been denied access to a US vendor’s advanced chipmaking equipment

SMIC is reportedly developing its 2nd generation 7nm class process that can be used to produce smartphone processors. The new report states that SMIC is conducting research on 5nm and 3nm processes. The research is conducted in-house by the company’s team of researchers and developers. The team is led by one of the CEOs, Liang Mong-Song, who is a well-known scientist. The team leader worked for TSMC and Samsung. He is considered one of the brightest minds in the semiconductor industry.

The rather instructive news is that the US sanctions regime has not been able to completely stop SMC’s progress in developing advanced 7nm chips. This may have seriously slowed the company down, but a number of factors are working in the company’s favor to overcome the challenges.

SMIC is currently the fifth largest contract chip manufacturer in the industry. He lost access to advanced wafer production tools, which severely limited his ability to implement new production technologies. As a result of the sanctions, SMIC was unable to obtain extreme ultraviolet (EUV) lithography tools from ASML. However, it relied solely on deep ultraviolet (DUV) lithography for its 7nm class 2nd generation node.

ASML Twinscan NXT:2000i lithography machines are currently the best tools available to SMIC. They can etch with production resolution up to 38 nm. The level of accuracy is sufficient to print 38-nanometer metal steps using a binary template for 7-nanometer-class nodes. According to AML and IMEC, metal spacings are reduced to 30-32 nm at 5 nm and 21-24 nm at 3 nm.

Multipatterns are another option to achieve ultra-small feature sizes that cannot use EUV. This is a complex process that increases cycle times and can impact efficiency, as well as wear and tear on production equipment. The cost of using multiple patterns is also quite high. SMIC uses triplet, quadruple, or sometimes quintuple simulations to achieve lower resolution. The development of the 3nm-class DUV-only manufacturing process is a significant milestone for SMIC. It is not yet known how the chip will work in the products.

Source: Port Altele

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