The PCI-SIG announced the previous PCIe 7.0 specification, the most advanced version of the local I / O bus, which will arrive at a stratospheric speed in a premiere that will not occur until 2025.

PCI Express is the basis of today’s computer architecture as it is used both for internal interconnection in integrated circuits of motherboards (chipsets), for communication of components such as CPU, and for connection of external cards (GPU, SSD, sound, networks …) pierced in corresponding slots or connectors. Here is a guide to this bus in case you want to make it.

PCIe 7.0 announced

You are probably still using a solution under PCIe 3.0, the most widely used version of the standard. But the technology industry is not resting, PCIe 4.0 has already been adopted and PCIe 5.0 began its deployment this year, as soon as Intel supports it with the Alder Lake platform and AMD will do so soon with AM4. Another version, 6.0, was announced last January and now another one is coming.

The announcement of specifications for PCIe 7.0 has arrived at the event PCI-SIG 2022 Developer Conference where the organization responsible for this standard celebrates its 30th anniversary. Its major improvement, as with previous standards, is the double the bandwidth compared to the previous one up to a total output of 128GT / s in one lane (x1).

This means that in a PCIe x16 slot, such as those that use dedicated graphics cards, theoretical bi-directional performance can increase up to 512 GB / s. Another example of great performance would be SSDs or Ethernet drives, up to 800 Gbe for data-intensive segments.

In addition to increasing performance, further developments are expected, such as lower latency, superior RAS capabilities or I / O virtualization enhancements to meet the growing needs of the industry. The coding scheme will also be improved PAM4 released in version 6.0 to increase transfer speeds.

This is what really allows the specification to achieve such a large bandwidth. It technically modulates signals at four levels and wraps two bits of information into a serial channel in the same amount of time. This PAM4 scheme is widely used in more powerful corporate networks such as InfiniBands, and we have also seen it in the GDDR6 graphics memory.

Further improvements should come from smaller physical size of the bus, which would allow the production of smaller cards and not the monstrous sizes that we find – for example – in today’s top dedicated graphics. This is understandable if more efficient cooling systems are achieved, as the new generations of NVIDIA and AMD graphics will be big energy eaters.

As is often the case with new standards, it will initially focus on solutions data centers, industrial, automotive, military and aerospace applications. It will not reach consumers until a few years later. There are still no components (graphics cards and SSDs) that take advantage of PCIe 5.0, and even PCIe 4.0 is still in the minority compared to the millions of boards that use version 3.0.

In any case, PCIe 7.0 is already up and running, and it’s important because in the future it will become the only one of its kind for computer architecture once the old ISAs, AGPs, the original PCIs, or less and less SATAs disappear. .