Heat is one of the great enemies of semiconductors, and in recent years it has become a very real problem affecting both Intel and AMD processors. With Zen 4, this problem has become even more apparent, as we told you in our analysis even the Ryzen 5 7600X reached 89 degrees C with a 360mm AIO liquid cooling kit.

AMD has always been clear on this issue. Sunnyvale acknowledged that the high temperatures of the Ryzen 7000 processors were caused by the problem transistor densityand also to Reducing CPU chiplet size. It is a subject that I already explained to you then and it is not difficult to understand.

With Zen 4, TSMC jumped to the 5nm node, which made it possible to increase the transistor density in the CPU chiplet and reduce its size. of 4.1 billion transistors which had a Zen 3 where we went 6.57 billion transistors in Zen 4 and the CPU chiplet size dropped from 74mm2 to 71mm2.

More transistors equals more heat generated and in a smaller space which facilitates its accumulation and reduces the useful scattering area, which greatly complicates cooling. This is why the Zen 4 processors reached such high temperatures even with high-performance cooling systems, because the dissipation area was very limited and the high concentration of transistors increased the heat.

AMD is going to continue betting on chiplets, so this problem will only increase with future generations of Ryzen processors. Another big litmus test AMD faces is the jump to the 3nm node, and according to David McAfee, corporate vice president and general manager of AMD’s client division, confirmed this realityhe said that transistor density will increase and that will be important find new ways to cope with the high concentration of heat derived from the use of chips with a high density of transistors.

He did not specify anything specifically, he said that they are actively working with TSMC on this issue. I think the use additional silicon structures or even complete non-functional chips to aid in distraction tasks Those would be the best options. AMD has already resorted to this to implement, for example, a 3D stacked cache, which is accompanied by two blocks of structural silicon sitting on the cores.